Techniques in which electronic components are joined with the use of solder with spacers provided with a specific height and interposed therebetween have been known. For instance, a technique for an electronic device in which a semiconductor device (semiconductor package) and a substrate are joined with the use of solder and in which spacers (which may be referred to as stand-off members, supporting members, or the like) are interposed between the semiconductor device and the substrate has been known.
Japanese Laid-open Patent Publication No. 2000-332473 and Japanese Laid-open Patent Publication No. 2006-237369 are examples of related art.
By the interposition of spacers between electronic components that are joined with the use of solder, a gap between the electronic components may be restrained from becoming smaller than a specified value and occurrence of squashing of solder joints, short circuits between adjoining solder joints, and the like may be restrained.
When contact is made between the spacers and the electronic components after the solder joining with the provision of the spacers, however, there is fear that stresses, strain, and the like caused by the contact may cause a decrease in connection strength in the solder joints, a decrease in reliability of connection between the electronic components, and the like.